1. Field of the Invention
This invention relates to a method of manufacturing semiconductor devices and, more particularly, to a method of writing lot numbers used for product management on semiconductor substrates.
2. Description of the Related Art
Recently, the density of active and passive elements integrated on a semiconductor substrate to form semiconductor circuits has remarkably increased. Correspondingly, the structure of circuits formed on the surface of a semiconductor wafer (hereinafter referred to simply as a "wafer") is extremely complicated. For example, in a planar process, a wafer is exposed to an oxidizing atmosphere at a high temperature to form an SiO.sub.2 layer having a uniform thickness on the surface of the wafer. This SiO.sub.2 layer has masking effects with respect to the diffusion of donor or acceptor impurity atoms. This layer is precisely processed by the photo-etching technique. This process is repeated a number of times to form an integrated multilayer semiconductor circuit.
In the process of manufacturing semiconductor substrates on which integrated circuits are formed in this manner, before the formation of circuit patterns, lot numbers are assigned to regions separate from the regions in which the circuit patterns are formed. The lot numbers are read by an optical means for management of the characteristics of products, the number of products and so on.
A conventional method of printing lot numbers and a relating printing structure will be described below.
Referring to FIG. 10, a character printing area 2 in which a lot number is to be printed and a circuit area 3 in which circuit patterns are to be formed are placed on a wafer 1. A predetermined lot number pattern 4 such as that shown in FIG. 11 is formed in the character printing area 2. Thereafter, an insulating layer 5 such as a polysilicon layer is formed over the whole surface of the wafer 1, and a metallic layer 6 such as an Al layer is formed on the insulating layer 5 as shown in FIG. 12, thereby enabling an integrated multilayer semiconductor circuit to be formed. In FIG. 12, only one insulating layer 5 and only one metallic layer 6 are formed, but several insulating layers and as many as several tens of metallic layers are formed in an actual process.
The character printing area 2 in which the lot number pattern 4 is formed is placed in a region to avoid interference with the circuit area 3 for the wafer 1. For example, as shown in FIG. 10, the character printing area 2 is placed opposite to the orientation flat 1a of the wafer 1 or in the vicinity of the orientation flat 1a.
FIG. 13 schematically shows an apparatus for printing lot numbers and for forming circuit patterns. First, in a resist application unit 7, a resist is applied to the surface of the wafer 1. Next, the wafer 1 is thereafter moved as indicated by the broken line in FIG. 13 to expose the circuit area 3 in a mask aligner 8, and to expose the character printing area 2 in a printing exposure unit 9. Thereafter, both the areas 2 and 3 are simultaneously developed in a development unit 10. The resist in the areas 2 and 3 is removed so as to expose the wafer 1. Then etching erodes portions of the wafer 1 corresponding to circuit pattern portions and lot number pattern portions, thereby forming recesses of the circuit pattern and the lot number pattern.
Thereafter, process steps of forming a metallic layer, applying the resist, exposure, development, etching and so on are repeated to form a plurality of layers of circuit patterns.
In this process, lot number patterns 4 etched as described above are read from the wafers 1 by an optical means for lot recognition.
However, circuit pattern lamination after etching patterns in the wafer 1 is effected over the whole surface of the wafer 1 including the character printing area 2 without being limited to the circuit area 3. That is, an undesirable layer is formed over the lot number pattern 4 which has already been formed suitably by the first etching. For this reason, a signal S.sub.1 obtained by reading the encoded lot number pattern 4a along the line B--B with an optical sensor of a printed code reader (not shown) has a large variation in level, as shown in FIG. 14. In FIG. 14, Vf represents the full scale.
This may be because extraneous materials are formed by chemical reaction at the interface between the metallic layer and the insulating layer, and cause irregular reflection at the time of reading with the optical sensor, adding noise components to the read signal S.sub.1. The accuracy in reading the lot number pattern 4a is therefore reduced.
As described above, the conventional process entails a problem in that irregular reflection is caused by extraneous materials existing at a layer interface in the character printing area 2, and noise components are thereby added to the read signal S.sub.1, resulting in a reduction in lot number reading accuracy and, hence, difficulty in correctly conducting product management.